The present invention relates to a semiconductor device and a control method for the semiconductor device. The present invention relates in particular to a semiconductor memory device including memory cells and a control method not requiring external control of refresh operation when performing hidden-refresh on memory cells in the semiconductor memory device that require refresh operation in order to retain data such as DRAM data.
In recent years, the logic circuit scale in system LSI is becoming increasingly larger to keep pace with more sophisticated system performance. The larger circuit scale in turn, requires a large capacity memory within the system LSI so that there are an increasing number of system LSIs which contain internal DRAM macros.
In contrast to memories such as SRAM that do not require refresh, using memories such as DRAM that require refresh in order to retain memories have the following issues. A first issue is that a memory controller is required in order to regulate the memory refresh. A second issue is that performance deteriorates due to long data access times caused by refresh period interrupts. A third issue is that using plural memory banks requires limiting bank allocation so that full random access is impossible. The above issues must therefore be resolved.
To resolve these problems, DRAM devices are being developed on a practical level to internally control the refresh in an operation hidden from the outside.
Japanese Patent Application Publication No. 2001-357670 describes as a first technology of the related art, a DRAM memory circuit with hidden-refresh operation. Here, an internal timer within the memory measures the time required for retaining data in the memory cell by refresh operation, and generates a refresh request at each required period in order to activate an internal sense amplifier or word line of an internal memory core. The operation when an access request from outside the memory conflicts with this refresh operation (so-called butting) is described. First of all, when an external access request for read or write operation was sent during the internal refresh operation, that external access request is temporarily buffered, and the read or write operation executed according to the external access request after the refresh operation was completed. Also, if the internal timer generated a refresh request while executing read or write, then that refresh request is temporarily buffered, and the refresh operation is then executed after the external access operation (read or write) was completed. Activating the memory core unit in this way, prevents butting (conflicts) between external access and refresh operation by utilizing an arbiter circuit that gives priority to the preceding operation.
Japanese Patent Application Publication No. 2002-74945 describes as a second technology of the related art, a semiconductor memory device that performs hidden-refresh using a synchronous type DRAM synchronized to operate from an externally supplied clock. The operation timing of the semiconductor memory device performing the hidden-refresh in the synchronous type DRAM performs the hidden-refresh described in Japanese Patent Application Publication No. 2002-74945 is shown in FIG. 9. In FIG. 9, “CLK” is the clock signal externally supplied to the semiconductor memory device, “ADD” is the address externally supplied to the semiconductor memory device, and “COMM” is the command externally supplied to the semiconductor memory device from the outside.
Also, the “timer” is a signal output from the timer for counting the refresh periods. The timer includes an internal oscillator and so can also operate asynchronously from the external clock when the external clock has stopped. The timer output signal transitions to low level when reset; and the timer output signal outputs a high-level output signal upon counting up to the required period for refresh. The device performs refresh operation when the timer output signal transitions to high level, and the timer output signal returns to low level when the refresh operation ends. The “Ref address” is the address for performing refresh. The “RA” denotes a low-state array core activation signal, “SE and Word line” denotes a sense amplifier and word line activation signal, “CA” denotes a column activation signal, and “DBUS” indicates data for the bus between the memory cell array and the external input/output terminals. In FIG. 9, the command COMM input to the DRAM in the t0 through t3 cycle is “NOP, and the memory is in non-select standby state not performing read or write. A time overflow occurs during the t0 cycle and the timer output signal rises to high level. Refresh occurs at the next t1 cycle in response to the rise of this timer output signal. The Ref address output by the refresh address generator circuit at this time is AFC1 and so the AFC1 address is selected to generate a low-state array core activation signal RA, to activate the word line and sense amplifier, and to refresh the memory cell. When the refresh operation is complete, the refresh address generator circuit counts the address up to the Ref address AFC2.
After a fixed amount of time elapses, in the to cycle, the timer once again overflows and the timer output signal transitions to high level the same as in the t1 cycle. However, the command COMM input in the tn cycle is the write command “WE” and so gives priority to read/write operation rather than the refresh operation. In other words, among refresh operations and read/write requests from the outside, priority is given to read/write request operations from the outside. The RA input via the external address A0 is therefore activated during the tn cycle. The write data D0 input at the same time generates a column activation signal (CA) and the D0 input via the bus is written into the cell. FIG. 9 showed the case where the write command was input during the tn cycle and write operation performed but even in cases where the read command was input during the tn cycle, priority is given to read operation rather than refresh operation, and the refresh operation executed during the CLK cycle after finishing these externally requested operations. In these synchronous type circuits, the trigger that starts DRAM core operation in each cycle is the CLK edge (pulse), and the read, write and refresh operations are configured so as to complete within one cycle. Active operation supports two-cycle specifications so hidden-refresh can be performed. In other words, read and write operations initiated from the outside appear to usually require two cycles, but internally initiated read and write operations effectively end within one cycle period. Refresh can be performed within the remaining one cycle so there is no need to be aware that a refresh cycle is externally initiated and hidden-refresh can be executed.
The cycle time required in active read or write operation can be expressed by the following (operation time) formula (I) even assuming specifications for achieving full random access operation such as in SRAM devices even with either of the related art technology in Japanese Patent Application Publication No. 2001-357670 and Japanese Patent Application Publication No. 2002-74945.Operation cycle time=(read or write operation time)+(refresh operation time)  formula (1)